1. Technical Field
Embodiments of the present invention relate to a semiconductor circuit technology, and more particularly, to a delay apparatus and a delay locked loop circuit and a semiconductor memory apparatus using the same.
2. Related Art
In general, clocks that are used in a semiconductor memory apparatus have been used as references to match the timing of operations, and have been used to achieve high-speed operation without the occurrence of errors. When the clock that is input from the outside of the semiconductor memory apparatus is used inside the semiconductor memory apparatus, a clock skew due to an internal circuit, that is, a time delay, is generated. In order to compensate for the time delay such that an internal clock and an external clock have the same phase, a delay locked loop circuit is generally used.
As shown in FIG. 1, a delay locked loop circuit according to the related art includes a first clock buffer 11, a second clock buffer 12, a clock divider 13, a first delay line 14, a second delay line 15, a third delay line 16, a shift register 17, a first driver 20, a second driver 21, a delay model 22, a phase comparator 19, and a shift controller 18. The first clock buffer 11 receives an inverted external clock/CLK and generates a first internal clock FCLK synchronized with a falling edge of an external clock CLK. The second clock buffer 12 receives the external clock CLK and generates a second internal clock RCLK synchronized with a rising edge of the external clock CLK. The clock divider 13 divides the second internal clock RCLK by 1/N (N is a positive number) and outputs a delay monitoring clock DLY_IN and a reference clock REF_CLK. The first delay line 14 receives and delays the first internal clock FCLK. The second delay line 15 receives and delays the second internal clock RCLK. The third delay line 16 receives and delays the delay monitoring clock DLY_IN. The shift register 17 determines a delay amount by each of the first to third delay lines 14 to 16. The first driver 20 responds to a delay locked signal DLL_LOCK and drives the output IFCLK of the first delay line 14 so as to generate a first delay locked loop clock FCLK_DLL. The second driver 21 responds to the delay locked signal DLL_LOCK and drives the output IRCLK of the second delay line 15 so as to generate a second delay locked loop clock RCLK_DLL. The delay model 22 allows the output FB_DLY of the third delay line 16 to pass through the same delay path as an actual clock path and outputs the output FB_DLY of the third delay line 16 as a feedback clock FB_CLK. The phase comparator 19 compares the phase of the feedback clock FB_CLK with the phase of the reference clock REF_CLK and outputs a phase detecting signal CTRL. The shift controller 18 responds to the phase detecting signal CTRL, and outputs shift control signals SR and SL to control a shift direction of the shift register 17 and the delay locked signal DLL_LOCK indicating that a delay locking operation has been performed.
The delay model 22 includes a dummy clock buffer, a dummy output buffer, a dummy load, and the like, and is also referred to as a replica circuit. The first to third delay lines 14 to 16, the shift register 17, and the shift controller 18 are collectively referred to as a register controlled delay part 10.
The first to third delay lines 14 to 16 have the same structure. Among the first to third delay lines 14 to 16, the third delay line 16 includes a plurality of unit delays (UD) 16-1, and link circuits (not shown) that determine the number of unit delays among the plurality of unit delays 16-1, which an input signal passes through, in accordance with the output of the shift register 17, as shown in FIG. 2.
The operation of the delay locked loop circuit according to the related art that has the above-described structure will now be described.
At the time of an initial operation, that is, at a timing when a reset signal is enabled, the delay monitoring clock DLY_IN passes through only one of the unit delays set in advance to be adjusted for the initial state of the third delay line 16, passes through the delay model 22, and is output as the feedback clock FB_CLK.
The phase comparator 19 compares rising edges of the reference clock REF_CLK and the feedback clock FB_CLK and outputs the phase detecting signal CTRL.
The shift controller 18 outputs the shift control signals SR and SL in response to the phase detecting signal CTRL.
The shift register 17 determines a delay amount by each of the first to third delay lines 14 to 16 in response to the shift control signals SR and SL. If the shift control signal SR is input, the shift register 17 shifts a register value to the right side, and if the shift control signal SL is input, the shift register 17 shifts the register value to the left side. In this way, the shift register 17 adjusts the delay amount.
Then, the shift controller 18 outputs the delay locked signal DLL_LOCK indicating that a delay locking operation has been performed at a timing when the feedback clock FB_CLK and the reference clock REF_CLK have the least amount of jitter.
The first and second drivers 20 and 21 drive the output IFCLK of the first delay line 14 and the output IRCLK of the second delay line 15 in response to the delay locked signal DLL_LOCK, which generates the first delay locked loop clock FCLK_DLL and the second delay locked loop clock RCLK_DLL that are synchronized with the external clock CLK.
The delay operation according to the related art will now be described in detail with reference to FIGS. 3A to 4B.
The first to third delay lines 14 to 16 are constructed such that if the delay locked loop circuit is initialized, an input signal, that is, the delay monitoring clock DLY_IN is output through the last unit delay, which cannot be changed.
As shown in FIG. 3A, it is assumed that the phase of the feedback clock FB_CLK is earlier than the phase of the reference clock REF_CLK by “D”. In this case, the feedback clock FB_CLK needs to be delayed by “D” so as to synchronize with the reference clock REF_CLK. Accordingly, a delay amount is increased by increasing the number of unit delays which the feedback clock FB_CLK passes through, starting from the last unit delay of the third delay line 16.
As shown in FIG. 3B, it is assumed that the phase of the feedback clock FB_CLK is slightly later than the phase of the reference clock REF_CLK. As described above, since the third delay line 16 uses only the last unit delay during an initial operation, the delay amount cannot be decreased any more. Accordingly, in order for the feedback clock FB_CLK to synchronize with the reference clock REF_CLK, the feedback clock FB_CLK needs to be delayed for almost a time of period tCK. Since the delay amount by all of the unit delays does not exceed a time of period tCK, the maximum unit delays are used in the case shown in FIG. 3B.
As shown in FIG. 3C, it is assumed that the phase of the reference clock REF_CLK is slightly later than the phase of the feedback clock FB_CLK. At this time, the third delay line 16 uses only the last unit delay, and the minimum unit delay is used in the case shown in FIG. 3C.
Meanwhile, as shown in FIG. 4A, when a change in PVT (Process/Voltage/Temperature) is generated after the delay locking operation is performed, that is, the phase of the feedback clock FB_CLK synchronizes with the phase of the reference clock REF_CLK, the phase of the feedback clock FB_CLK may be slightly later than the phase of the reference clock REF_CLK. The first to third delay lines 14 to 16 and the delay model 22 include inverters or logic gates, each delay value is changed according to the change in PVT, and the delay value is increased when the voltage is decreased.
As shown in FIG. 4A, since the phase of the feedback clock FB_CLK is later than the phase of the reference clock REF_CLK by “D2” after the delay locking operation is performed, the delay amount by the delay lines needs to be decreased, such that the feedback clock FB_CLK synchronizes with the reference clock REF_CLK.
However, if the delay amount “D1” by the unit delay is smaller than the delay amount to be decreased, the feedback clock FB_CLK cannot synchronize with the reference clock REF_CLK, and the constant phase difference “D2−D1” is generated, as shown in FIG. 4B.
As described above, in the delay locked loop circuit according to the related art, the delay amount during the initial operation is locked. If the locked delay amount is smaller than the delay amount to be compensated for, the two clocks cannot be synchronized with each other, and thus the functionality of the delay locked loop is decreased. When the phase difference between the two clocks, which cannot be corrected, departs from an operating range of the semiconductor memory apparatus, a defective operation occurs not only in the delay locked loop circuit but also in the semiconductor memory apparatus using the same.